As silicon process technologies produce smaller and smaller device geometries, and with higher and higher levels of integration as well as increasing clock rates on interconnects, on-die impedance compensation circuits take on a more and more prominent role. Due to the factors mentioned above, it has been found to be necessary to update the compensation circuits more frequently. The updates are required in order to account for changes in device temperature, changing voltages, and process variations. These circuits are typically updated during device operation at periodic intervals. This poses a potential problem for devices operating at high data rates, particularly for those using interface protocols that require continuous data transmission to maintain synchronization. The problem is that when the impedance compensation is updated, the change in impedance may cause signal integrity problems on the interconnect, resulting in potential data corruption.
One protocol that requires continuous data transmission in order to maintain synchronization is the Serial ATA protocol (Serial ATA Specification rev. 1.0 released Jun. 28, 2001). This protocol allows communication between two devices such as a disk controller and a disk drive. The Serial ATA specification provides for a serial interconnect using differential pair signaling. The Serial ATA specification further provides for periodic transmission of alignment primitives. The alignment primitive is a predetermined pattern of bits of a predetermined length that is recognized by devices coupled to the interconnect. The alignment primitive allows devices that have lost synchronization to recover bit-boundary alignment.
The Serial ATA protocol, as well as some other protocols, do not set aside any time for impedance compensation update operations. What is needed is a capability of performing impedance compensation update operations without adversely disturbing the continuous flow of data.